CY2DP1502 buffer equivalent, 1:2 lvpecl fanout buffer.
* One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
* Translates any single-ended input signal to 3.3 V LVPECL level.
The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew.
Image gallery
Download